Superjunction structures are well known in the art and are described, for example, by Fujihira, “Theory of Semiconductor Superjunction Devices,” Jpn J. Appl. Phys., Vol. 36 (1997), pp. 6254-6262; Fujihira and Miyasaka, “Simulated Superior Performance of Semiconductor Superjunction Devices,” Proc. of 1998 Symposium on Power Semiconductor Devices & ICs, Kyoto, Japan, pp. 423-426; Strollo and Napoli, “Optimal ON-Resistance Versus Breakdown Voltage Tradeoff in Superjunction Power Devices. A Novel Analytical Model,” IEEE Transactions on Electron Devices, Vo. 48, No. 9, September 2001, pp. 2161-2167; and Gerald Deboy, “The Superjunction Principle as Enabling Technology for Advanced Power Solutions”, IEEE ISIE 2005, Jun. 20-23, 2005, Dubrovnik, Croatia, pages 469-472. In its simplest form, superjunction structures employ a number of alternatively arranged P and N doped semiconductor layers or regions, with the condition that the doping of these layers are charge-balanced, or Na*Wa=Nd*Wd, in which Na and Nd are the doping concentrations of the P and N layers, and Wa, Wd, the widths of these same layers. Current flow through such superjunction structures is for the most part parallel to the planes of the P-N junctions. Superjunction structures are often employed in high voltage (and high power) semiconductor (SC) devices in order to obtain comparatively high breakdown voltages while minimizing series ON-resistance. The superjunction structures facilitate this desirable combination of properties. Superjunction devices are also available on the open market, as for example, the CoolMOS™ family of devices produced by Infineon of Villach, Austria.
FIG. 1 illustrates prior art JFET superjunction device 20 comprising interleaved array 21 of P-type layers 22 and N-type layers 24 of thickness d, with intervening PN junctions 23. Layers 22, 24 are of the same semiconductor material, e.g., silicon, but with different doping. In FIG. 1, in response to bias voltage VDS, drain-source current ID flows left-to-right through, for example, N-type layers 24 that are coupled at their left ends to drain contact 25 and at their right ends to source contact 26. P-type layers 22 are coupled to gate electrode 27. When appropriately biased, gate potential VGS applied across PN junctions 23 causes drain-source current ID to increase or decrease at constant VDS depending upon the amount of gate bias VGS. Such operation is conventional.
FIG. 2 illustrates prior art TMOS device 30 employing superjunction structure 31 in the drift space between channel 47 and drain 32. Device 30 comprises N+ substrate (e.g., drain) 32 on which has been formed superjunction structure 31 comprising multiple parallel vertically arranged N-type regions 33 and P-type regions 34, of for example silicon, with intervening PN junctions 35. Lower end 36 of superjunction structure 31 contacts substrate 32, which together with electrical contact 40 forms the drain of TMOS transistor 30. Device regions 37 are formed in upper portion 38 of superjunction structure 31. Device regions 37 include P-type body regions 42, P+ body contact regions 43 and N+ source regions 44 located in body regions 42. Gate dielectric 46 extends between source regions 44 above channel regions 47 located in the P-type body regions 42. Gate electrodes 49 overlie gate dielectric 46. Source and body contact 45 makes electrical contact to body contact regions 43 and sources 44. When device 30 is appropriately biased, current 50 flows between source contact 45 and source regions 44 into N-type drift regions 33 and on to substrate drain 32 and drain contact 40. P regions 34 extend from substrate 32 to body regions 42. N regions 33 form the carrier drift region communicating with drain 32. If width 53 of N region 33 and width 54 of P region 34 are properly chosen along with their respective doping densities, according to principles well known in the art, then the combination forms superjuction structure 31 wherein the source-drain breakdown voltage is increased compared to an otherwise identical device of similar drift region thickness 52, but without the alternating N and P regions. Alternatively, thickness 52 may be made smaller for the same breakdown voltage thereby providing lower ON-resistance, or a combination of such beneficial effects may be elected by favorably adjusting thickness 52 and the doping density of regions 33, 34. This is known in the art.
While the structures illustrated in FIGS. 1-2 are useful, it is desirable to improve their properties. Accordingly, there is a need for improved device structures and methods of fabrication that can provide improved performance. It is desirable to provide superjunction type semiconductor devices that offer, for example, improved carrier mobility while still being able to be fabricated using conventional processing equipment and process chemistry. Further it is desirable to provide an improved device structure and method of fabrication that is useful with a variety of semiconductor materials and useful for forming a wide variety of semiconductor devices in addition to the FET devices shown in FIGS. 1 and 2. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.